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LTC1390 8-Channel Analog Multiplexer with Serial Interface
FEATURES
s s
DESCRIPTIO
s s s s s s s s s
3-Wire Serial Digital Interface Data Retransmission Allows Series Connection with Serial A/D Converters Single 3V to 5V Supply Operation Analog Inputs May Extend to Supply Rails Low Charge Injection Low RON: 75 Max Low Leakage: 5nA Max Guaranteed Break-Before-Make TTL/CMOS Compatible for All Digital Inputs Cascadable to Allow Additional Channels Can Be Used as a Demultiplexer
The LTC(R)1390 is a high performance CMOS 8-to-1 analog multiplexer. It features a 3-wire digital interface with a bidirectional data retransmission feature, allowing it to be wired in series with a serial A/D converter while using only one serial port. The interface also allows several LTC1390s to be wired in series or parallel, increasing the number of MUX channels available using only a single digital port. All the above features are also valid when LTC1390 operates as a demultiplexer such as with a D/A converter. The LTC1390 features a typical RON of 45, typical switch leakage of 50pA, and guaranteed break-before-make operation. Charge injection is 10pC maximum. All digital inputs are TTL and CMOS compatible when operated from single or dual supplies. The inputs can withstand 100mA fault currents. The LTC1390 is available in 16-pin PDIP and narrow SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATI
s s s
S
Data Acquisition Systems Communication Systems Signal Multiplexing/Demultiplexing
TYPICAL APPLICATI
VCC VEE
VCC 1 2 3 4 ANALOG INPUTS 5 6 7 8 3-WIRE SERIAL INTERFACE TO MUX AND ADC 16 15 14 13 12 11 10 9 VCC 47k DATA CLK CS OPTIONAL A/D INPUT FILTER 1 2 3 8 7
S0 S1 S2 S3 S4 S5 S6 S7 LTC1390
V+ D V-
CS +IN -IN
VCC
DATA 2 DATA 1 CS CLK GND
ON-RESISTANCE ()
CLK LTC1096 6 DOUT 4 5 VREF GND
LTC1390 * TA01
U
ON-Resistance vs Analog Input Voltage
250 TA = 25C 200 V + = 3V V - = 0V 150 100 V + = 5V V - = - 5V 50 0 -5 -4 -3 -2 -1 0 1 2 3 4 ANALOG INPUT VOLTAGE, VS (V) 5
LTC1390 * TA02
UO
UO
1
LTC1390 ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW S0 S1 S2 S3 S4 S5 S6 S7 1 2 3 4 5 6 7 8 16 V + 15 D 14 V - 13 DATA 2 12 DATA 1 11 CS 10 CLK 9 GND
Total Supply Voltage (V + to V -) .............................. 15V Input Voltage Analog Inputs ........................ V - - 0.3V to V + + 0.3V Digital Inputs ........................................ - 0.3V to 15V Digital Outputs............................ - 0.3V to V + + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range ..................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1390CN LTC1390CS
N PACKAGE 16-LEAD PDIP
S PACKAGE 16-LEAD PLASTIC SO
TJMAX = 150C, JA = 70C/ W (N) TJMAX = 150C, JA = 100C/ W (S)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
V + = 5V, V - = - 5V, GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL Switch VANALOG RON Analog Signal Range On Resistance (Note 2) VS = 3.5V, ID = 1mA TMIN 25C TMAX
q
PARAMETER
CONDITIONS
MIN -5
TYP
MAX 5 75 75 120
UNITS V % %/C
45 20 0.5
RON vs VS RON vs Temperature IS(OFF) ID(OFF) ID(ON) Input VINH VINL IINL, IINH VOH VOL High Level Input Voltage Low Level Input Voltage Low or High Level Current High Level Output Voltage Low Level Output Voltage V+ = 5.25V V+ = 4.75V VIN = 5V, VIN = 0V V+ = 4.75V, IO = 10A V+ = 4.75V, IO = 360A V+ = 4.75V, IO = 0.5mA
q q q q q
Off Input Leakage Off Output Leakage On Channel Leakage
VS = 4V, VD = - 4V; VS = - 4V, VD = 4V Channel Off VS = 4V, VD = - 4V; VS = - 4V, VD = 4V Channel Off VS = VD = 4V Channel On
0.05
q
5 50 5 50 5 50
0.05
q
0.05
q
2.4 0.8 1 2.4 4.74 4.50 0.16 0.8
2
U
nA nA nA nA nA nA V V A V V V
W
U
U
WW
W
LTC1390
ELECTRICAL CHARACTERISTICS
V + = 5V, V - = - 5V, GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL Dynamic fCLK tON tOFF tOPEN OIRR OINJ CS(OFF) CD(OFF) Supply I+ I- Positive Supply Current Negative Supply Current All Logic Inputs Tied Together, VIN = 0V or VIN = 5V All Logic Inputs Tied Together, VIN = 0V or VIN = 5V
q q
PARAMETER Clock Frequency Enable Turn-On Time Enable Turn-Off Time Break-Before-Make Interval Off Isolation Charge Injection Source Off Capacitance Drain Off Capacitance
CONDITIONS
MIN
TYP
MAX 5
UNITS MHz ns ns ns dB
VS = 2.5V, RL = 1k, CL = 35pF VS = 2.5V, RL = 1k, CL = 35pF 35 VS = 2VP-P, RL = 1k, f = 100kHz RS = 0, CL = 1000pF, VS = 1V (Note 2)
260 100 155 70 2 5 10 15 15
400 200
10
pC pF pF
40 40
A A
V + = 3V, V - = GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL Switch VANALOG RON Analog Signal Range On Resistance (Note 2) VS = 1.2V, ID = 1mA TMIN 25C TMAX
q
PARAMETER
CONDITIONS
MIN 0
TYP
MAX 3 255 255 300
UNITS V % %/C
200 20 0.5
RON vs VS RON vs Temperature IS(OFF) ID(OFF) ID(ON) Input VINH VINL IINL, IINH VOH VOL High Level Input Voltage Low Level Input Voltage Low or High Level Current High Level Output Voltage Low Level Output Voltage V+ = 3.3V V+ = 2.7V VIN = 3V, VIN = 0V V+ = 2.7V, IO = 20A V+ = 2.7V, IO = 400A V+ = 2.7V, IO = 20A V+ = 2.7V, IO = 300A
q q q q q
Off Input Leakage Off Output Leakage On Channel Leakage
VS = 2.5V, VD = 0.5V; VS = 0.5V, VD = 2.5V (Note 3) Channel Off VS = 2.5V, VD = 0.5V; VS = 0.5V, VD = 2.5V (Note 3) Channel Off VS = VD = 0.5V, VS = VD = 2.5V (Note 3) Channel On
0.05
q
5 50 5 50 5 50
nA nA nA nA nA nA V
0.05
q
0.05
q
2.4 0.8 1 2 2.68 2.27 0.01 0.15 0.8
V A V V V V
3
LTC1390
ELECTRICAL CHARACTERISTICS
V + = 3V, V - = GND = 0V, TA = operating temperature unless otherwise noted.
SYMBOL Dynamic fCLK tON tOFF tOPEN OIRR OINJ CS(OFF) CD(OFF) Supply I+ Positive Supply Current All Logic Inputs Tied Together, VIN = 0V or VIN = 3V
q
PARAMETER Clock Frequency Enable Turn-On Time Enable Turn-Off Time Break-Before-Make Interval Off Isolation Charge Injection Source Off Capacitance Drain Off Capacitance
CONDITIONS
MIN
TYP
MAX 5
UNITS MHz ns ns ns dB
VS = 1.5V, RL = 1k, CL = 35pF (Note 4) VS = 1.5V, RL = 1k, CL = 35pF (Note 4) (Note 4) VS = 2VP-P, RL = 1k, f = 100kHz RS = 0, CL = 1000pF, VS = 1V (Note 2) 125
490 190 290 70 1 5 10 0.2
700 300
5
pC pF pF
2
A
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those beyond which the safety of the device may be impaired. Note 2: Guaranteed by design.
Note 3: Leakage current with a single 3V supply is guaranteed by correlation with the leakage current of the 5V supply. Note 4: Timing specifications with a single 3V supply is guaranteed by correlation with the timing specifications of the 5V supply.
TYPICAL PERFORMANCE CHARACTERISTICS
ON-Resistance vs Temperature
300 250
ON-RESISTANCE ()
200 150 100 50 0 0 10
V + = 3V V - = 0V VS = 1.2V
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
V + = 5V V - = - 5V VS = 0V
40 30 50 20 TEMPERATURE (C)
4
UW
60
LTC1390 * G01
Driver Output Low Voltage vs Output Current
6 5 4 DATA 1 3 2 DATA 2 1 0
70 0
Driver Output High Voltage vs Output Current
-1 -2 -3 -4 DATA 1 -5 -6 -7 2.0 TA = 25C V + = 5V V - = -5V DATA 2
TA = 25C V + = 5V V - = -5V
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT VOLTAGE (V)
LTC1390 * G02
2.5
4.0 3.5 3.0 OUTPUT VOLTAGE (V)
4.5
5.0
LTC1390 * G03
LTC1390
PIN FUNCTIONS
S0 to S7 (Pins 1 to 8): Analog Multiplexer Inputs/Analog Demultiplexer Outputs. GND (Pin 9): Digital Ground. Connect to system ground. CLK (Pin 10): System Clock (TTL/CMOS Compatible). The clock synchronizes the channel selection bits and the serial data transfer from Data 1 to Data 2. CS (Pin 11): Chip Select Input (TTL/CMOS Compatible). A logic high on this input enables LTC1390 to read in the channel selection bits and allow data transfer from Data 1 to Data 2. A logic low enables the desired channel for analog signal transmission and allows data transfer from Data 2 to Data 1. Data 1 (Pin 12): Bidirectional Digital Input/Output (TTL/ CMOS Compatible). Input for the channel selection bits. Data 2 (Pin 13): Bidirectional Digital Input/Output (TTL/ CMOS Compatible). V - (Pin 14): Negative Supply. D (Pin 15): Analog Multiplexer Output/Analog Demultiplexer Input. V + (Pin 16): Positive Supply.
APPLICATIO S I FOR ATIO
Multiplexer Operation
Figure 1 shows the block diagram of the components within the LTC1390 required for MUX operation. The LTC1390 uses Data 1 to select its 8 channels and a chip select input CS to switch on the selected channel as shown in Figure 2.
CLK DATA 1 CS CONTROL LOGIC 4-BIT SHIFT REGISTER
ANALOG INPUT
MUX BLOCK
ANALOG OUTPUT
LTC1390 * F01
Figure 1: Simplified Block Diagram of the MUX Operation
CLK
CS EN = HIGH DATA 1 ANY ANALOG INPUTS D
LTC1390 * F02
B2
B1
B0
tON
Figure 2: Multiplexer Operation
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W
U
U
U
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When CS is high, the input data on the Data 1 pin is latched into the 4-bit shift register on each rising clock edge. The input data consists of an "EN" bit and a string of three bits for channel selection. If "EN" bit is logic high as illustrated in the first input data sequence, it enables the selected channel. To ensure correct operation, the CS must be pulled low before the next rising clock edge. Once the CS is pulled low, all channels are simultaneously switched off to ensure a break-before-make interval. After a delay of tON, the selected channel is switched on allowing signal transmission. The selected channel remains on until the next falling edge of CS, and after a delay of tOFF, it terminates the analog signal transmission and subsequently allows the selection of the next channel. If "EN" bit is logic low, as illustrated in the second data sequence, it disables all channels and there will be no analog signal
EN = LOW B2 B1 B0
tOFF
5
LTC1390
APPLICATIO S I FOR ATIO
Table 1. Logic Table for Channel Selection
CHANNEL STATUS All Off S0 S1 S2 S3 S4 S5 S6 S7 EN 0 1 1 1 1 1 1 1 1 B2 X 0 0 0 0 1 1 1 1 B1 X 0 0 1 1 0 0 1 1 B0 X 0 1 0 1 0 1 0 1
transmission. Table 1 shows the various bit combinations for channel selection.
Digital Data Transfer Operation The block diagram of Figure 3 shows the components contained within the LTC1390 required for digital data transfer. Digital data transfer operation can be performed from Data 1 to Data 2 and vice versa as shown in Figure 4. When CS is high, Buffer 1 is enabled and Buffer 2 is disabled. The digital input data is fed into the 4-bit shift register and then shifted to the MUX switches for channel
CLK 4-BIT SHIFT REGISTER MUX SWITCHES
BUFFER 1
CS
DATA 1
BUFFER 2
Figure 3. Simplified Block Diagram of the Digital Data Transfer Operation
CLK 1 2 3 4
CS DATA 1 DATA 2 Hi-Z
DATA OUT DATA IN
DATA IN DATA OUT
LTC1390 * F04
Figure 4. Digital Data Transfer Operation
6
U
selection or to Data 2 via Buffer 1 for data transfer. Data appears at Data 2 after the fourth rising edge of the clock. When CS is low, Buffer 2 is enabled and Buffer 1 is disabled, thus digital input data is directly transferred from Data 2 to Data 1 without any clock delay. Multiplexer Expansion Several LTC1390s can be daisy-chained to expand the number of multiplexer inputs. No additional interface ports are required for the expansion. Figure 5 shows two LTC1390s connected at their analog outputs to form a 16to-1 multiplexer at the input to an LTC1286 A/D converter.
VCC VEE VCC 1 2 S0 V+ 16 1 2 VREF +IN VCC 8 15 S1 LTC1390 D 3 14 A S2 V- 4 13 S3 DATA 2 ANALOG 5 12 INPUTS S4 DATA 1 6 11 S5 CS 7 10 S6 CLK 8 9 S7 GND 1 2
DATA 2
W
U
U
7 CLK LTC1286 3 6 -IN DOUT 4 5 CS GND
VCC S0 S1 S2 16 V+ 15 LTC1390 D - 14 B V 13 DATA 2 12 DATA 1 11 CS 10 CLK 9 GND 47k
3 4
S3 ANALOG INPUTS 5 S4 6 S5 7 S6 8 S7
LTC1390 * F03
DATA CS CLK
LTC1390 * F05
Figure 5. Daisy-Chaining Two LTC1390s for Expansion
To ensure that only one channel is switched on at any one time, two sets of channel selection bits are needed for Data as shown in Figure 6. The first data sequence is used to switch off one MUX and the second data sequence is used to select one channel from the other MUX, or vice versa. In other words, if bit "ENA" is high and bit "ENB" is low, one channel of MUX A is switched on and all channels of MUX B are switched off. If bit "ENA" is low and bit "ENB" is high, all channels of MUX A are switched off and one channel of MUX B is switched on.
LTC1390
APPLICATIO S I FOR ATIO
CLK 1 2 3 4 5 6 7 8 CS
DATA
ENA
A2
A1
A0
ENB
B2
B1
B0 tSMPL
DIGITAL INPUT FROM LTC1390
Figure 6. Timing Diagram for Figure 5
TYPICAL APPLICATIONS N
Daisy-Chaining Five LTC1390s
BYPASS CAPACITOR FROM V + TO GND AND V - TO GND REQUIRED FOR EACH LTC1390 VCC VEE 1 2 S0 V+ 16 15 1 2 3 VCC
ANALOG INPUTS
S1 LTC1390 D 3 14 A S2 V- 4 13 S3 DATA 2 5 12 S4 DATA 1 6 11 S5 CS 7 10 S6 CLK 8 9 S7 GND 1 2 V+ 16
CLK LTC1286 6 -IN DOUT 4 5 CS GND
S0
ANALOG INPUTS
15 S1 LTC1390 D 3 - 14 B S2 V 4 13 S3 DATA 2 5 12 S4 DATA 1 6 11 S5 CS 7 10 S6 CLK 8 9 S7 GND 1 2 V+ 16
S0
ANALOG INPUTS
15 S1 LTC1390 D 3 14 C S2 V- 4 13 S3 DATA 2 5 12 S4 DATA 1 6 11 S5 CS 7 10 S6 CLK 8 9 S7 GND
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
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NULL BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z tDATA
LTC1390 * F06
W
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UU
tCONV DIGITAL OUTPUT FROM LTC1286
VREF +IN
VCC
8 7
VCC 47k
VCC VEE 1 2 S0 V+ 16
ANALOG INPUTS
15 S1 LTC1390 D 3 14 D S2 V- 4 13 S3 DATA 2 5 12 S4 DATA 1 6 11 S5 CS 7 10 S6 CLK 8 9 S7 GND 1 2 3 4 V+ 16
S0
ANALOG INPUTS
5 6 7 8
15 S1 LTC1390 D 14 E S2 V- 13 S3 DATA 2 12 S4 DATA 1 11 S5 CS 10 S6 CLK 9 S7 GND
DATA* CS CLK *REQUIRES FIVE 4-BIT CHANNEL SELECTION DATA BYTES
LTC1390 * TA03
7
LTC1390
TYPICAL APPLICATIONS N
Interfacing LTC1390 with LTC1257 for Demultiplex Operation
VCC VEE OPTIONAL D/A OUTPUT FILTER
1 2 3 4 ANALOG OUTPUTS 5 6 7 8 DATA CLK CS
S0 S1 S2 S3 S4 S5 S6 S7 LTC1390
PACKAGE DESCRIPTION
0.130 0.005 (3.302 0.127) 0.015 (0.381) MIN
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.125 (3.175) MIN
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
0.053 - 0.069 (1.346 - 1.752) 0 - 8 TYP
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
RELATED PARTS
PART NUMBER LTC201A/LTC202/LTC203 LTC221/LTC222 LTC128x/LTC129x DESCRIPTION Micropower, Low Charge Injection, Quad CMOS Analog Switches Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches Serial A/Ds with Integral MUXs
LT/GP 0695 10K * PRINTED IN THE USA
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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V+ D V-
16 15 14 13 12 11 10 9 VCC 47k VCC 1 2 VCC CLK LTC1257 7 VOUT DIN 3 6 LOAD VREF 4 5 GND DOUT 8
DATA 2 DATA 1 CS CLK GND
LTC1390 * F03
Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead Plastic DIP
0.045 - 0.065 (1.143 - 1.651) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9
0.255 0.015* 0.065 (6.477 0.381) (1.651) TYP 0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076) 1 2 3 4 5 6 7 8
S Package 16-Lead Plastic SOIC
0.004 - 0.010 (0.101 - 0.254) 16 15 14
0.386 - 0.394* (9.804 - 10.008) 13 12 11 10 9
0.050 (1.270) TYP
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157* (3.810 - 3.988)
1
2
3
4
5
6
7
8
COMMENTS Each Channel is Independently Controlled Parallel Controlled with Data Latches
(c) LINEAR TECHNOLOGY CORPORATION 1995

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